Description: 这个给QuartusII初学者用的，里面很清楚的通过几个例子来告诉怎么运用QuartusII．
实验1：Quartus入门
实验2：简单的组合逻辑电路设计
实验3：七段数码管显示
实验4：BCD码显示及运
实验5：触发器和计数器
实验6：存储器的设计
实验7：基于DE2 的SOPC系统开发附录：-This QuartusII beginners to use, which is very clear through several examples to tell how the use of QuartusII. Experiment 1: Quartus entry Experiment 2: a simple combinational logic circuit design of experiment 3: Seven-Segment LED display experiment 4: BCD code display and shipped experiment 5: flip-flops and counters experiment 6: the design of memory test 7: Based on DE2 the SOPC System Development Appendix: Platform: |
Size: 754688 |
Author:yulieyar |
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Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as Platform: |
Size: 82944 |
Author:lkiwood |
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Description: 3 simple AVR assembler code to use seven segment display. These 3 codes realy simple way using seven segment display. these are using in my microprocessor classes.
Wert deney1.asm -> no scan
Wert Deney2.asm -> Scan but BCD
Werrt Deney3.asm -> Scan with BCD.
By Basri KUL-3 simple AVR assembler code to use seven segment display. These 3 codes realy simple way using seven segment display. these are using in my microprocessor classes.
Wert deney1.asm-> no scan
Wert Deney2.asm-> Scan but BCD
Werrt Deney3.asm-> Scan with BCD.
By Basri KUL Platform: |
Size: 9216 |
Author:cooluser |
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Description: BCD 译码器,将8421BCD码转换成七段共阴A~G-Decoder BCD to Seven-Segment 8421BCD code into a total of Yin A ~ G Platform: |
Size: 794624 |
Author:祁才君 |
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Description: BCD码到七段数码管的显示程序，已成功综合，仿真通过-BCD code to the Seven-Segment LED display procedures have been successfully integrated, simulation through Platform: |
Size: 111616 |
Author:chendongkui |
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Description: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code Platform: |
Size: 1024 |
Author:吴金通 |
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Description: VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描，而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works Platform: |
Size: 144384 |
Author:夏强 |
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Description: 七段显示译码器
因为计算机输出的是BCD码，要想在数码管上显示十进制数，就必须先把BCD码转换成 7 段字型数码管所要求的代码。我们把能够将计算机输出的BCD码换成 7 段字型代码，并使数码管显示出十进制数的电路称为“七段字型译码器”。
-Seven-segment display decoder because the computer output is BCD code, in order to display in the digital tube decimal number, it must first convert the BCD code fonts 7 segment digital pipes required by code. We can replace the computer output, 7 segment BCD code font code, and make the digital control circuit shows a decimal number called the " Seven-Segment decoder fonts." Platform: |
Size: 3072 |
Author:jlz |
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Description: ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. -ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. Platform: |
Size: 1024 |
Author:hassan |
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Description: this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder-this is a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder Platform: |
Size: 1024 |
Author:hassan |
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Description: BCD\七段显示译码器
数码管段显示发光二级管是共阴连结，所以显示高电平有效，即哪一段的驱动信号为高电平，则对应段发亮-BCD \ seven-segment display decoder digital tube sections show light-emitting diode is a link to a total of yin, it showed high and effective, that is what section of the drive signal is high, then the corresponding segment bright Platform: |
Size: 17408 |
Author:bryan |
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Description: 此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。-This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field. Platform: |
Size: 1024 |
Author:王柔毅 |
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Description: 用vhdl语言编译一个码制转换
四位二进制->BCD码，然后将BCD码->七段显示器码。
（1）当输入为0~9的数时，其十位数为0，个位数=输入。
当输入为10~15的数时，其十位数为1，个位数=输入-10。
（2）然后将十位和个位的BCD码转换为七段显示码
-Vhdl language used to compile a binary code system conversion of four-> BCD code, then BCD code-> seven-segment display code. (1) When the input is a number from 0 to 9, its ten digits 0 digits = input. When the input is 10 to 15 the number, the tens digit is 1, digits = input-10. (2) and then ten and a bit BCD code is converted to seven segment display code Platform: |
Size: 326656 |
Author:宋子皓 |
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Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data. Platform: |
Size: 56320 |
Author:will li |
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